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Our People > Corina E. Tanasa

 

Corina E. Tanasa
Scientific Patent Advisor

Address:
Birch, Stewart, Kolasch & Birch, LLP
Suite 100 East
8110 Gatehouse Road
Falls Church, VA  22042
USA

Telephone: +1-703-205-8000
Facsimile: +1-703-205-8050
E-mail: cet@bskb.com

Education: Bard College (B.A. Physics and Mathematics, 2000); Massachusetts Institute of Technology (M.S. Electrical Engineering and Computer Science, 2002); The George Washington University Law School (JD, anticipated, 2011).

Bar Admissions: Registered to practice before the U.S. Patent and Trademark Office (limited recognition).

Experience:

  • Patent Engineer at Birch, Stewart, Kolasch & Birch, LLP since 2005. Supports patent prosecution in the area of electrical engineering, including semiconductors, analog circuitry, digital circuitry, digital signal processing. Applies electrical engineering principles and specialized knowledge to assist in the technical study, research and analysis of technologies involved in the preparation and prosecution of patent applications.
  • Core Technology and Process Engineer (semiconductors) at Applied Materials INC., 2003-2005.
  • Research Affiliate in the Department of Micro and Nanotechnology,  Technical University of Denmark, June-July 2000.
  • Research Intern at Stanford Nanofabrication Facility, Stanford University, various years.

Patents:

  • USP 7,112,763, " Method and apparatus for low temperature pyrometry useful for thermally processing silicon wafers ", Aaron Hunter, Rajesh S. Ramanujam, Balasubramanian Ramachandran, Corina Elena Tanasa, Tarpan Dixit. Also published as WO2006047062.
     
  • US Patent Application 20060066193, "Lamp array for thermal processing exhibiting improved radial uniformity", Joseph M. Ranish, Corina E. Tanasa, Sundar Ramamurthy, Claudia Lai, Ravi Jallepally, Ramachandran Balasubramanian, Aaron M. Hunter, Agus Tjandra, Norman Tam. Also published as WO2006036644.


Selected Publications:

  • "Low Temperature Processing for Ni-Si Technology", A. Hunter, C. Tanasa, J. Ranish, R. Achutharaman, S. Ramamurthy, R, Jallepally, A. Tiandra, N. Tam, International IEEE RTP Conference, 2005.
  • "RTP Uniformity Improvement Through  Simulation", J. Ranish, C. Tanasa, A. Hunter, R. Achutharaman, , S. Ramamurthy, R, Jallepally, A. Tiandra. International IEEE RTP Conference, 2004, Portland, Oregon.
  • "Very High Hole Mobility Strained Si/SiGe Layers for p-Type Heterostructure-Based PMOS Devices at Room and Low Temperatures", C. Tanasa, D.A.Antoniadis, C.W.Leitz, M.L.Lee, E.A.Fitzgerald, Judy Hoyt, 2003 Electronic Materials Conference, Salt Lake, Utah.
  • " Fabrication and Actuation of Customized Nanotweezers with a 25nm Gap", P.Boggild, T.M.Hansen, C. Tanasa, F.Grey, Nanotechnology 12, 331 (2001).
  • " Charging and Discharging of Electron Beam Resist Films", M. Bai, R. F. W. Pease, C. Tanasa, M.McCord, D. S. Pickard, D. Meisburger, Journal of Vacuum Science and Technology B, 17, 2893 (1999).
  • " Resist Charging in Electron Beam Lithography", M. Bai, R. F. W. Pease, C. Tanasa, M. A. McCord, D.S. Pickard, D. Meisburger, N. Berglund, 18th Annual BACUS Symposium on Photomask Technology and Management, SPIE 1998.

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Office Information
:: Falls Church, Virginia Office

Practice Areas
:: Electrical Practice
© 2007 Birch, Stewart, Kolasch & Birch, LLP - Last revised: 26 March  2007 - webmaster@bskb.com