About Us

Corina E. Tanasa

Associate

Address
Birch, Stewart, Kolasch & Birch, LLP
Suite 100 East
8110 Gatehouse Road
Falls Church, VA 22042
USA

Telephone +1-703-205-8000
Facsimile +1-703-205-8050
E-mail

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Bar Admissions
2012, District of Columbia; registered to practice before the U.S. Patent and Trademark Office. Not licensed in Virginia.

Education
Bard College (B.A. Physics and Mathematics, 2000); Massachusetts Institute of Technology (M.S. Electrical Engineering and Computer Science, 2002); The George Washington University Law School (J.D., 2011).

Memberships
American Intellectual Property Law Association.

Experience
Corina Tanasa has been with BSKB since 2005, supporting patent prosecution in the area of electrical engineering, including semiconductors, analog circuitry, digital circuitry, and digital signal processing. Ms. Tanasa applies electrical engineering principles and specialized knowledge to assist in the technical study, research and analysis of technologies involved in the preparation and prosecution of patent applications. Ms. Tanasa also has experience as a Core Technology and Process Engineer (semiconductors) at Applied Materials INC., a Research Affiliate in the Department of Micro and Nanotechnology, Technical University of Denmark, and as a Research Intern at Stanford Nanofabrication Facility, Stanford University.

Patents
  • US Patent 7,112,763, "Method and apparatus for low temperature pyrometry useful for thermally processing silicon wafers ", Aaron Hunter, Rajesh S. Ramanujam, Balasubramanian Ramachandran, Corina Elena Tanasa, Tarpan Dixit. Corresponding foreign patent applications EP1809111 (A2), JP2008518472 (T), CN101128716 (A), KR20070060158 (A).
  • US Patent 7,509,035, "Lamp array for thermal processing exhibiting improved radial uniformity", Joseph M. Ranish, Corina E. Tanasa, Sundar Ramamurthy, Claudia Lai, Ravi Jallepally, Ramachandran Balasubramanian, Aaron M. Hunter, Agus Tjandra, Norman Tam.
Selected Publications
  • "Low Temperature Processing for Ni-Si Technology", A. Hunter, C. Tanasa, J. Ranish, R. Achutharaman, S. Ramamurthy, R, Jallepally, A. Tiandra, N. Tam, International IEEE RTP Conference, 2005.
  • "RTP Uniformity Improvement Through Simulation", J. Ranish, C. Tanasa, A. Hunter, R. Achutharaman, , S. Ramamurthy, R, Jallepally, A. Tiandra. International IEEE RTP Conference, 2004, Portland, Oregon.
  • "Very High Hole Mobility Strained Si/SiGe Layers for p-Type Heterostructure-Based PMOS Devices at Room and Low Temperatures", C. Tanasa, D.A. Antoniadis, C.W. Leitz, M.L. Lee, E.A. Fitzgerald, Judy Hoyt, 2003 Electronic Materials Conference, Salt Lake, Utah.
  • " Fabrication and Actuation of Customized Nanotweezers with a 25nm Gap", P. Boggild, T.M. Hansen, C. Tanasa, F. Grey, Nanotechnology 12, 331 (2001).
  • " Charging and Discharging of Electron Beam Resist Films", M. Bai, R. F. W. Pease, C. Tanasa, M. McCord, D. S. Pickard, D. Meisburger, Journal of Vacuum Science and Technology B, 17, 2893 (1999).
  • " Resist Charging in Electron Beam Lithography", M. Bai, R. F. W. Pease, C. Tanasa, M. A. McCord, D.S. Pickard, D. Meisburger, N. Berglund, 18th Annual BACUS Symposium on Photomask Technology and Management, SPIE 1998.